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IS61VPS25636A IS61LPS25636A IS61VPS51218A IS61LPS51218A 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
FEATURES
* Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * Burst sequence control using MODE input * Three chip enable option for simple depth expansion and address pipelining * Common data inputs and data outputs * Auto Power-down during deselect * Single cycle deselect * Snooze MODE for reduced-power standby * JTAG Boundary Scan for PBGA package * Power Supply LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5% * JEDEC 100-Pin TQFP, 119-ball PBGA, and 165-ball PBGA packages * Lead-free available
ISSI
MAY 2005
(R)
DESCRIPTION The ISSI IS61LPS/VPS25636A and IS61LPS/
VPS51218A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LPS/VPS25636A is organized as 262,144 words by 36 bits and the IS61LPS/VPS51218A is organized as 524,288 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency 250 2.6 4 250 200 3.1 5 200 Units ns ns MHz
Copyright (c) 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
1
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
BLOCK DIAGRAM
MODE Q0 A0'
ISSI
(R)
CLK
CLK
A0
BINARY COUNTER
ADV ADSC ADSP CE CLR Q1 A1' A1
256Kx36; 512Kx18 MEMORY ARRAY
16/17 18/19
18/19 A D Q
ADDRESS REGISTER
CE CLK 36, or 18 36, or 18
GW BWE BW(a-d) x18: a,b x36: a-d
DQ(a-d) BYTE WRITE REGISTERS
CLK
D
Q
CE CE2 CE2 D Q
2/4/8
ENABLE REGISTER
CE CLK
INPUT REGISTERS
CLK
OUTPUT REGISTERS
CLK OE
36, or 18 DQa - DQd
D
Q
ENABLE DELAY REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
165-PIN BGA
165-Ball, 13x15 mm BGA 1mm Ball Pitch, 11x15 Ball Array
ISSI
(R)
119-PIN BGA
119-Ball, 14x22 mm BGA 1mm Ball Pitch, 7x17 Ball Array
BOTTOM VIEW BOTTOM VIEW
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
3
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
ISSI
(R)
119 BGA PACKAGE PIN CONFIGURATION-256K X 36 (TOP VIEW)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ 2 A CE2 A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A NC TMS 3 A A A Vss Vss Vss BWc Vss NC Vss BWd Vss Vss Vss MODE A TDI 4 ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1* A0* VDD A TCK 5 A A A Vss Vss Vss BWb Vss NC Vss BWa Vss Vss Vss NC A TDO 6 A A A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A NC NC 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol A A0, A1 ADV ADSP ADSC GW CLK CE, CE2 BWx (x=a-d) BWE Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor Address Status Controller Global Write Enable Synchronous Clock Synchronous Chip Select Synchronous Byte Write Controls Byte Write Enable Symbol OE ZZ MODE TCK, TDO TMS, TDI NC DQa-DQd DQPa-Pd VDD VDDQ Vss No Connect Data Inputs/Outputs Output Power Supply Power Supply Output Power Supply Ground Pin Name Output Enable Power Sleep Mode Burst Sequence Selection JTAG Pins
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
ISSI
(R)
119 BGA PACKAGE PIN CONFIGURATION
512KX18 (TOP VIEW)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC NC VDDQ 2 A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A TMS 3 A A A Vss Vss Vss BWb Vss NC Vss Vss Vss Vss Vss MODE A TDI 4 ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1* A0* VDD NC TCK 5 A A A Vss Vss Vss Vss Vss NC Vss BWa Vss Vss Vss NC A TDO 6 A A A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC 7 VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol A A0, A1 ADV ADSP ADSC GW CLK CE, CE2 BWx (x=a,b) BWE Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor Address Status Controller Global Write Enable Synchronous Clock Synchronous Chip Select Synchronous Byte Write Controls Byte Write Enable Symbol OE ZZ MODE TCK, TDO TMS, TDI NC DQa-DQb DQPa-Pb VDD VDDQ Vss No Connect Data Inputs/Outputs Output Power Supply Power Supply Output Power Supply Ground Pin Name Output Enable Power Sleep Mode Burst Sequence Selection JTAG Pins
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
5
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
ISSI
10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa A A
(R)
165 PBGA PACKAGE PIN CONFIGURATION
256K X 36 (TOP VIEW)
1 A B C D E F G H J K L M N P R NC NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE 2 A A NC DQc DQc DQc DQc Vss DQd DQd DQd DQd NC NC NC 3 CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWc BWd Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A 5 BWb BWa Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC TDI TMS 6 CE2 CLK Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC A1* A0* 7 BWE GW Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC TDO TCK 8 ADSC OE Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol A A0, A1 ADV ADSP ADSC GW CLK CE, CE2, CE2 Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor Address Status Controller Global Write Enable Synchronous Clock Synchronous Chip Select Symbol BWE OE ZZ MODE TCK, TDO TMS, TDI NC DQx DQPx VDD VDDQ
Vss
Pin Name Byte Write Enable Output Enable Power Sleep Mode Burst Sequence Selection JTAG Pins No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply
Isolated Output Power Supply 3.3V/2.5V Ground
BWx (x=a,b,c,d) Synchronous Byte Write Controls
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
165 PBGA PACKAGE PIN CONFIGURATION
512K X 18 (TOP VIEW)
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE 2 A A NC DQb DQb DQb DQb Vss NC NC NC NC NC NC NC 3 CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWb NC Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A 5 NC BWa Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC TDI TMS 6 CE2 CLK Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC A1* A0* 7 BWE GW Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC TDO TCK 8 ADSC OE Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A
ISSI
11 A NC DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC A A
(R)
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol A A0, A1 ADV ADSP ADSC GW CLK CE, CE2, CE2 BWx (x=a,b) Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor Address Status Controller Global Write Enable Synchronous Clock Synchronous Chip Select Synchronous Byte Write Controls Symbol BWE OE ZZ MODE TCK, TDO TMS, TDI NC DQx DQPx VDD VDDQ
Vss
Pin Name Byte Write Enable Output Enable Power Sleep Mode Burst Sequence Selection JTAG Pins No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply
Isolated Output Power Supply 3.3V/2.5V Ground
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
7
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
PIN CONFIGURATION 100-PIN TQFP (256K X 36)
A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
ISSI
(R)
DQPc
DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A
DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa
DQPc
DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A
A A CE CE2 BWd BWc BWb BWa A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa
(3 Chip-Enable option)
(2 Chip-Enable option)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Controller Address Status Synchronous Processor Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable Vss ZZ DQa-DQd DQPa-DQPd GW MODE OE VDD VDDQ Synchronous Data Input/Output Parity Data Input/Output Synchronous Global Write Enable Burst Sequence Mode Selection Output Enable 3.3V/2.5V Power Supply Isolated Output Buffer Supply: 3.3V/2.5V Ground Snooze Enable
A ADSC ADSP ADV BWa-BWd BWE
CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
PIN CONFIGURATION 100-PIN TQFP (512K X 18)
A A CE CE2 NC NC BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
ISSI
(R)
NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A A CE CE2 NC NC BWb BWa A VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
MODE A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A
(3 Chip-Enable Option)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Controller Address Status Synchronous Processor Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable Synchronous Clock Synchronous Data Input/Output DQPa-DQPb GW MODE OE VDD VDDQ Vss ZZ Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8 Synchronous Global Write Enable Burst Sequence Mode Selection Output Enable 3.3V/2.5V Power Supply Isolated Output Buffer Supply: 3.3V/2.5V Ground Snooze Enable
A ADSC ADSP ADV BWa-BWb BWE CLK DQa-DQb
CE, CE2, CE2 Synchronous Chip Enable
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A
(2 Chip-Enable Option)
9
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
TRUTH TABLE(1-8)
OPERATION Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Snooze Mode, Power-Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADDRESS CE CE2 CE-2 ZZ None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current H L L L L X L L L L L X X H H X H X X H H X H X X H X H X L L L L L X X X X X X X X X X X X X L X L X X H H H H H X X X X X X X X X X X X L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC ADV L X X L L X X X L L L H H H H H H H H H H H H X X X X X X X X X X X L L L L L L H H H H H H WRITE OE X X X X X X X X L H H H H H H L L H H H H L L X X X X X X L H X L H L H L H X X L H L H X X
ISSI
CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
(R)
NOTE: 1. X means "Don't Care." H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-d) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa's and DQPa. BWb enables WRITEs to DQb's and DQPb. BWc enables WRITEs to DQc's and DQPc. BWd enables WRITEs to DQd's and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE
Function Read Read Write Byte 1 Write All Bytes Write All Bytes 10 GW H H H H L BWE H L L L X BWa X H L L X BWb X H H L X BWc X H H L X BWd X H H L X
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00
ISSI
(R)
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol TSTG PD IOUT VIN, VOUT VIN VDD Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to Vss for I/O Pins Voltage Relative to Vss for for Address and Control Inputs Voltage on VDD Supply Relative to Vss Value Unit -55 to +150 C 1.6 W 100 mA -0.5 to VDDQ + 0.5 V -0.5 to VDD + 0.5 V -0.5 to 4.6 V
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
11
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
OPERATING RANGE (IS61LPSXXXXX)
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 3.3V + 5% 3.3V + 5% VDDQ 3.3V / 2.5V + 5% 3.3V / 2.5V + 5%
ISSI
(R)
OPERATING RANGE (IS61VPSXXXXX)
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 2.5V + 5% 2.5V + 5% VDDQ 2.5V + 5% 2.5V + 5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Vss VIN VDD
(1)
Test Conditions IOH = -4.0 mA (3.3V) IOH = -1.0 mA (2.5V) IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V)
Min. 2.4 -- 2.0 -0.3 -5 -5
Max. -- 0.4 VDD + 0.3 0.8 5 5
2.5V Min. Max. 2.0 -- 1.7 -0.3 -5 -5 -- 0.4 VDD + 0.3 0.7 5 5
Unit V V V V A A
Output Leakage Current Vss VOUT VDDQ, OE = VIH
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-250 MAX x18 x36 275 300 275 300 -200 MAX x18 x36 250 275 250 275
Symbol Parameter ICC AC Operating Supply Current
Test Conditions
Temp. range
Unit mA
Device Selected, Com. OE = VIH, ZZ VIL, Ind. All Inputs 0.2V or VDD - 0.2V, Cycle Time tKC min. Device Deselected, VDD = Max., All Inputs VIL or VIH, ZZ VIL, f = Max. Com. Ind.
ISB
Standby Current TTL Input
150 150
150 150
150 150
150 150
mA
ISBI
Standby Current CMOS Input
Device Deselected, Com. VDD = Max., Ind. VIN VSS + 0.2V or VDD - 0.2V f=0 ZZ>VIH Com. Ind.
100 105
100 105
100 105
100 105
mA
ISB2
Sleep Mode
50 60
50 60
50 60
50 60
mA
Note: 1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits 100A maximum leakage current when tied to VSS + 0.2V or VDD - 0.2V.
12
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Rev. A 04/29/05
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
ISSI
(R)
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2
AC TEST LOADS
317
ZO = 50 Output
3.3V
50
OUTPUT 5 pF Including jig and scope
Figure 2
351
1.5V
Figure 1
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
13
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
ISSI
(R)
2.5V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4
2.5 I/O OUTPUT LOAD EQUIVALENT
1,667
ZO = 50 Output
2.5V
50
OUTPUT 5 pF Including jig and scope
Figure 4
1,538
1.25V
Figure 3
14
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-250 Symbol fMAX tKC tKH tKL tKQ tKQX
(2) (2,3)
ISSI
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc
(R)
Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time ZZ High to Power Down ZZ Low to Power Down
Min. -- 4.0 1.7 1.7 -- 0.8 0.8 -- -- 0 -- 1.2 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 -- --
Max. 250 -- -- -- 2.6 -- -- 2.6 2.6 -- 2.6 -- -- -- -- -- -- -- -- -- -- 2 2
-200 Min. Max. -- 5 2 2 -- 1.5 1 -- -- 0 -- 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 -- -- 200 -- -- -- 3.1 -- -- 3.0 3.1 -- 3.0 -- -- -- -- -- -- -- -- -- -- 2 2
tKQLZ tOEQ
tKQHZ(2,3) tOELZ tAS tWS tCES tAVS tDS tAH tWH tCEH tAVH tDH tPDS tPUS
(2,3) (2,3)
tOEHZ
Note: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2.
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15
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
READ/WRITE CYCLE TIMING
tKC
ISSI
(R)
CLK
tSS tSH tKH tKL
ADSP is blocked by CE inactive
tSH
ADSP
tSS
ADSC initiate read
ADSC
tAVS tAVH
Suspend Burst
ADV
tAS tAH
Address
RD1
tWS tWH
RD2
RD3
GW
tWS tWH
BWE
BWx
tCES tCEH
CE Masks ADSP
CE
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
CE2
tCES tCEH
CE2
tOEQ tOEHZ
OE
tOELZ tOEQX tKQX
DATAOUT
High-Z
tKQLZ tKQ
1a
2a
2b
2c
2d
tKQHZ
DATAIN
High-Z Pipelined Read Single Read Burst Read Unselected
16
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
WRITE CYCLE TIMING
tKC
ISSI
(R)
CLK
tSS tSH tKH tKL
ADSP is blocked by CE inactive
ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS ADV
tAS tAH tAVH
Address
WR1
tWS tWH
WR2
WR3
GW
tWS tWH
BWE
tWS tWH tWS tWH
BWx
tCES tCEH
WR1
WR2 CE Masks ADSP
WR3
CE
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
CE2
tCES tCEH
CE2
OE High-Z
tDS tDH
DATAOUT
DATAIN
High-Z
1a
BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d
3a
Single Write
Burst Write
Write
Unselected
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17
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol ISB2 tPDS tPUS tZZI tRZZI Parameter Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SNOOZE current ZZ inactive to exit SNOOZE current Conditions ZZ Vih Min. -- -- 2 -- 0 Max. 60 2 -- 2 --
ISSI
Unit mA cycle cycle cycle ns
(R)
SNOOZE MODE TIMING
CLK
tPDS ZZ setup cycle tPUS ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2 tRZZI
All Inputs (except ZZ)
Deselect or Read Only
Deselect or Read Only Normal operation cycle
Outputs (Q)
High-Z Don't Care
18
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
The IS61LPS/VPSxxxxxx products have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (The TQFP package not available.) This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels.
ISSI
(R)
TEST ACCESS PORT (TAP) - TEST CLOCK
The test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left disconnected if the TAP is not used. The pin is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register. For information on instruction register loading, see the TAP Controller State Diagram. TDI is internally pulled up and can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register.
DISABLING THE JTAG FEATURE
The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (Vss) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up, the device will start in a reset state which will not interfere with the device operation.
TAP CONTROLLER BLOCK DIAGRAM
0 Bypass Register
2 TDI Selection Circuitry
1
0 Selection Circuitry TDO
Instruction Register
31 30 29
...
2
1
0
Identification Register
x
.....
Boundary Scan Register*
2
1
0
TCK TMS
TAP CONTROLLER
19
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IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register.
ISSI
(R)
is set LOW (VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 75-bit-long register and the x18 configuration also has a 75-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins. (See TAP Controller Block Diagram) At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as previously described. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path.
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size (x18) 3 1 32 75 Bit Size (x36) 3 1 32 75
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has vendor code and other information described in the Identification Register Definitions table.
IDENTIFICATION REGISTER DEFINITIONS
Instruction Field Revision Number (31:28) Device Depth (27:23) Device Width (22:18) ISSI Device ID (17:12) ISSI JEDEC ID (11:1) ID Register Presence (0) 20 Description Reserved for version number. Defines depth of SRAM. 256K or 512K Defines width of the SRAM. x36 or x18 Reserved for future use. Allows unique identification of SRAM vendor. Indicate the presence of an ID register. 256K x 36 xxxx 00111 00100 xxxxx 00011010101 1 512K x 18 xxxx 01000 00011 xxxxx 00011010101 1
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
ISSI
(R)
TAP INSTRUCTION SET
Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; instead it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the CaptureDR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock runs more than an order of magnitude faster. Because of the clock frequency differences, it is possible that during the Capture-DR state, an input or output will under-go a transition. The TAP may attempt a signal capture while in transition (metastable state). The device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. To guarantee that the boundary scan register will capture the correct signal value, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). To insure that the SRAM clock input is captured correctly, designs need a way to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is not an issue, it is possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. Because EXTEST is not implemented in the TAP controller, this device is not 1149.1 standard compliant. The TAP controller recognizes an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is a difference between the instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon powerup or whenever the TAP controller is given a test logic reset state.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
SAMPLE-Z
The SAMPLE-Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.
RESERVED
These instructions are not implemented but are reserved for future use. Do not use these instructions.
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IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
ISSI
(R)
INSTRUCTION CODES
Code 000 Instruction EXTEST Description Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
001 010 011 100
IDCODE SAMPLE-Z RESERVED SAMPLE/PRELOAD
101 110 111
RESERVED RESERVED BYPASS
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset 1 0 Run Test/Idle 0 1 1 Select DR 0 Capture DR 0 Shift DR 1 Exit1 DR 0 1 Select IR 0 1 Capture IR 0 Shift IR 1 Exit1 IR 0 Pause IR 1 0 Exit2 IR 1 1
0 1
0 1
Pause DR 0 1 0 1 Exit2 DR 1 Update DR 0
0
1
Update IR 0
22
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IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
TAP Electrical Characteristics Over the Operating Range(1,2)
Symbol VOH1 VOH2 VOL1 VOL2 VIH VIL IX Notes:
1. All Voltage referenced to Ground. 2. Overshoot: VIH (AC) VDD +1.5V for t tTCYC/2, Undershoot: VIL (AC) 0.5V for t tTCYC/2, Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
ISSI
Min. 1.7 2.1 -- -- 1.7 -0.3 Max. -- -- 0.7 0.2 VDD +0.3 0.7 10 V V V V V V A
(R)
Parameter Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current
Test Conditions IOH = -2.0 mA IOH = -100 A IOL = 2.0 mA IOL = 100 A
Units
VSS V I VDDQ
-10
TAP AC ELECTRICAL CHARACTERISTICS(1,2) (OVER OPERATING RANGE)
Symbol Parameter tTCYC fTF tTH tTL tTMSS tTDIS tCS tTMSH tTDIH tCH tTDOV tTDOX Notes:
1. Both tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Min. 100 -- 40 40 10 10 10 10 10 10 -- 0
Max. -- 10 -- -- -- -- -- -- -- -- 20 --
Unit ns MHz ns ns ns ns ns ns ns ns ns ns
TCK Clock cycle time TCK Clock frequency TCK Clock HIGH TCK Clock LOW TMS setup to TCK Clock Rise TDI setup to TCK Clock Rise Capture setup to TCK Rise TMS hold after TCK Clock Rise TDI Hold after Clock Rise Capture hold after Clock Rise TCK LOW to TDO valid TCK LOW to TDO invalid
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IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
ISSI
(R)
TAP AC TEST CONDITIONS (2.5V/3.3V)
Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage Vtrig 0 to 2.5V/0 to 3.0V 1ns 1.25V/1.5V 1.25V/1.5V 1.25V/1.5V 1.25V/1.5V
TAP Output Load Equivalent
50 Vtrig
TDO Z0 = 50 20 pF GND
TAP TIMING
1 tTHTH TCK
2 tTLTH
3
4
5
6
tTHTL tMVTH tTHMX
TMS tDVTH tTHDX TDI tTLOV TDO tTLOX DON'T CARE UNDEFINED
24
Integrated Silicon Solution, Inc. -- 1-800-379-4774
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IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
119 BGA BOUNDARY SCAN ORDER (256K X 36)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Signal Bump Name ID A A A A A A A DQa DQa DQa DQa DQa DQa DQa DQa DQa ZZ DQb 2R 3T 4T 5T 6R 3B 5B 6P 7N 6M 7L 6K 7P 6N 6L 7K 7T 6H Bit # 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Signal Bump Name ID DQb DQb DQb DQb DQb DQb DQb DQb A A ADV ADSP ADSC OE BWE GW CLK A 7G 6F 7E 7D 7H 6G 6E 6D 6A 5A 4G 4A 4B 4F 4M 4H 4K 6B Bit # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Signal Bump Name ID BWa BWb BWc BWd CE2 CE A A DQc DQc DQc DQc DQc DQc DQc DQc DQc NC 5L 5G 3G 3L 2B 4E 3A 2A 2D 1E 2F 1G 2H 1D 2E 2G 1H 5R Bit # 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
ISSI
DQd DQd DQd DQd DQd DQd DQd DQd DQd MODE A A A A A1 A0 2K 1L 2M 1N 1P 1K 2L 2N 2P 3R 2C 3C 5C 6C 4N 4P
(R)
Signal Bump Name ID
119 BGA BOUNDARY SCAN ORDER (512K X 18)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 Signal Bump Name ID A A A A A A A DQa DQa DQa DQa ZZ DQa 2R 2T 3T 5T 6R 3B 5B 7P 6N 6L 7K 7T 6H Bit # 14 15 16 17 18 19 20 21 22 23 24 25 26 Signal Bump Name ID DQa DQa DQa DQa A A A ADV ADSP ADSC OE BWE GW 7G 6F 7E 6D 6T 6A 5A 4G 4A 4B 4F 4M 4H Bit # 27 28 29 30 31 32 33 34 35 36 37 38 39 Signal Bump Name ID CLK A BWa BWb CE2 CE A A DQb DQb DQb DQb NC 4K 6B 5L 3G 2B 4E 3A 2A 1D 2E 2G 1H 5R Bit # 40 41 42 43 44 45 46 47 48 49 50 51 Signal Bump Name ID DQb DQb DQb DQb DQb MODE A A A A A1 A0 2K 1L 2M 1N 2P 3R 2C 3C 5C 6C 4N 4P
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IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
ISSI
Bit # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal Name DQd DQd DQd DQd DQd DQd DQd DQd DQd A A A A A1 A0 1J 1K 1L 1M 2J 2K 2L 2M 1N 3P 3R 4R 4P 6P 6R
(R)
165 PBGA BOUNDARY SCAN ORDER (x 36)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Signal Bump Name ID MODE NC A A A A A A A A ZZ DQa DQa DQa DQa DQa DQa DQa DQa DQa 1R 6N 11P 8P 8R 9R 9P 10P 10R 11R 11H 11N 11M 11L 11K 11J 10M 10L 10K 10J Bit # 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal Name DQb DQb DQb DQb DQb DQb DQb DQb DQb NC A A ADV ADSP ADSC OE BWE GW CLK NC Bump ID 11G 11F 11E 11D 10G 10F 10E 10D 11C 11A 10A 10B 9A 9B 8A 8B 7A 7B 6B 11B Bit # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Signal Name NC CE2 BWa BWb BWc BWd CE2 CE A A NC DQc DQc DQc DQc DQc DQc DQc DQc DQc Bump ID 1A 6A 5B 5A 4A 4B 3B 3A 2A 2B 1B 1C 1D 1E 1F 1G 2D 2E 2F 2G Bump ID
26
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
ISSI
Bit # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal Name DQb DQb DQb DQb DQb NC NC NC NC A A A A A1 A0 1J 1K 1L 1M 1N 2K 2L 2M 2J 3P 3R 4R 4P 6P 6R
(R)
165 PBGA BOUNDARY SCAN ORDER (x 18)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Signal Bump Name ID MODE NC A A A A A A A A ZZ NC NC NC NC NC DQa DQa DQa DQa 1R 6N 11P 8P 8R 9R 9P 10P 10R 11R 11H 11N 11M 11L 11K 11J 10M 10L 10K 10J Bit # 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal Name DQa DQa DQa DQa DQa NC NC NC NC A A A ADV ADSP ADSC OE BWE GW CLK NC Bump ID 11G 11F 11E 11D 11C 10F 10E 10D 10G 11A 10A 10B 9A 9B 8A 8B 7A 7B 6B 11B Bit # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Signal Name NC CE2 BWa NC BWb NC CE2 CE A A NC NC NC NC NC NC DQb DQb DQb DQb Bump ID 1A 6A 5B 5A 4A 4B 3B 3A 2A 2B 1B 1C 1D 1E 1F 1G 2D 2E 2F 2G Bump ID
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IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O) Commercial Range: 0C to +70C
Configuration 256Kx36 250 IS61LPS25636A-250TQ IS61LPS25636A-250B2 IS61LPS25636A-250B3 IS61LPS25636A-200TQ IS61LPS25636A-200B2 IS61LPS25636A-200B3 IS61LPS51218A-250TQ IS61LPS51218A-250B2 IS61LPS51218A-250B3 200 IS61LPS51218A-200TQ IS61LPS51218A-200B2 IS61LPS51218A-200B3 100 TQFP, 3CE 119 PBGA 165 PBGA 100 TQFP, 3CE 119 PBGA 165 PBGA 100 TQFP, 3CE 119 PBGA 165 PBGA 100 TQFP, 3CE 119 PBGA 165 PBGA Frequency Order Part Number Package(1)
ISSI
(R)
200
512Kx18 250
Industrial Range: -40C to +85C
Configuration 256Kx36 250 IS61LPS25636A-250TQI IS61LPS25636A-250B2I IS61LPS25636A-250B3I IS61LPS25636A-200TQI IS61LPS25636A-200TQ2I IS61LPS25636A-200TQLI IS61LPS25636A-200B2I IS61LPS25636A-200B3I IS61LPS51218A-250TQI IS61LPS51218A-250B2I IS61LPS51218A-250B3I IS61LPS51218A-200TQI IS61LPS51218A-200TQ2I IS61LPS51218A-200TQLI IS61LPS51218A-200B2I IS61LPS51218A-200B3I 100 TQFP, 3CE 119 PBGA 165 PBGA 100 TQFP, 3CE 100 TQFP, 2CE 100 TQFP, 3CE, Lead-free 119 PBGA 165 PBGA 100 TQFP, 3CE 119 PBGA 165 PBGA 100 TQFP, 3CE 100 TQFP, 2CE 100 TQFP, 3CE, Lead-free 119 PBGA 165 PBGA Frequency Order Part Number Package(1)
200
512Kx18 250
200
Note: 1. For 100 TQFP, 2CE option contact SRAM Marketing at sram@issi.com
28
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
IS61VPS25636A, IS61LPS25636A, IS61VPS51218A, IS61LPS51218A
ORDERING INFORMATION (2.5V core/2.5V I/O) Commercial Range: 0C to +70C
Configuration 256Kx36 250 IS61VPS25636A-250TQ IS61VPS25636A-250B2 IS61VPS25636A-250B3 200 IS61VPS25636A-200TQ IS61VPS25636A-200B2 IS61VPS25636A-200B3 IS61VPS51218A-250TQ IS61VPS51218A-250B2 IS61VPS51218A-250B3 200 IS61VPS51218A-200TQ IS61VPS51218A-200B2 IS61VPS51218A-200B3 100 TQFP, 3CE 119 PBGA 165 PBGA 100 TQFP, 3CE 119 PBGA 165 PBGA 100 TQFP, 3CE 119 PBGA 165 PBGA 100 TQFP, 3CE 119 PBGA 165 PBGA Frequency Order Part Number Package(1)
ISSI
(R)
512Kx18 250
Industrial Range: -40C to +85C
Configuration 256Kx36 250 IS61VPS25636A-250TQI IS61VPS25636A-250B2I IS61VPS25636A-250B3I IS61VPS25636A-200TQI IS61VPS25636A-200TQ2I IS61VPS25636A-200TQLI IS61VPS25636A-200B2I IS61VPS25636A-200B3I IS61VPS51218A-250TQI IS61VPS51218A-250B2I IS61VPS51218A-250B3I IS61VPS51218A-200TQI IS61VPS51218A-200TQ2I IS61VPS51218A-200B2I IS61VPS51218A-200B3I 100 TQFP, 3CE 119 PBGA 165 PBGA 100 TQFP, 3CE 100 TQFP, 2CE 100 TQFP, 3CE, Lead-free 119 PBGA 165 PBGA 100 TQFP, 3CE 119 PBGA 165 PBGA 100 TQFP, 3CE 100 TQFP, 2CE 119 PBGA 165 PBGA Frequency Order Part Number Package(1)
200
512Kx18 250
200
Note: 1. For 100 TQFP, 2CE option contact SRAM Marketing at sram@issi.com
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 04/29/05
29
PACKAGING INFORMATION
Plastic Ball Grid Array Package Code: B (119-pin)
ISSI
b (119X)
7 6 5 4 32 1 A B C D E F G H J K L M N P R T U
(R)
E
A
30
D
D2
D1
e
A2 E2 A3 A1
E1
A4
SEATING PLANE
MILLIMETERS Sym.
N0. Leads A A1 A2 A3 A4 b D D1 D2 E E1 E2 e -- 0.50 0.80 1.30 0.60 21.80 19.40 13.80 11.90
INCHES Min. Max.
Notes:
Min.
119
Max.
2.41 0.70 1.00 1.70 0.90 22.20 19.60 14.20 12.10
-- 0.020 0.032 0.051 0.024 0.858 0.764 0.543 0.469
0.095 0.028 0.039 0.067 0.035 0.874 0.772 0.559 0.476
1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusion and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
0.56 BSC
0.022 BSC
20.32 BSC
0.800 BSC
7.62 BSC 1.27 BSC
0.300 BSC 0.050 BSC
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 02/12/03
PACKAGING INFORMATION
Ball Grid Array Package Code: B (165-pin)
TOP VIEW
A1 CORNER 1
A B C D E F G H J K L M N P R
b (165X)
ISSI
BOTTOM VIEW
A1 CORNER 9 8 7 6 5 4 3 2 1
A B C D
(R)
2
3
4
5
6
7
8
9
10
11
11 10
e
E F G
D D1
H J K L M N P R
e E1 E A2 A1 A
BGA - 13mm x 15mm
MILLIMETERS Sym.
N0. Leads A A1 A2 D D1 E E1 e b -- 0.25 -- 14.90 13.90 12.90 9.90 -- 0.40
INCHES Min. Nom. Max.
165
Notes: 1. Controlling dimensions are in millimeters.
Min.
Nom. Max.
165 -- 0.33 0.79 15.00 14.00 13.00 10.00 1.20 0.40 -- 15.10 14.10 13.10 10.10 -- 0.50
-- 0.010 -- 0.587 0.547 0.508 0.390 -- 0.016
-- 0.031 0.591 0.551 0.512 0.394 0.039 0.018
0.047 -- 0.594 0.555 0.516 0.398 -- 0.020
0.013 0.016
1.00
0.45
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 06/11/03
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package) Package Code: TQ
ISSI
D D1
(R)
E
E1
N
1
C e SEATING PLANE
L1 L
A2 A1 b
A
Millimeters Symbol Min Max Ref. Std. No. Leads (N) 100 A -- 1.60 -- 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. C 0o 7o 0o 7o
Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max 128 -- 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o
Inches Min Max
-- 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o
Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PK13197LQ Rev. D 05/08/03

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